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Mitigation of Co-channel Interference on ASIC Inter-Chip CommunicationsField/context: ASIC and Core interconnection design, wireline communications, and multiuser detection.
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Background and problem: The higher on the data transmission speed between the serial the ASIC chips can produce its co-channel interference (crosstalk) exponential increased. It eventually threats the ASICs’ function performance or possibly pollutes their design function totally. Solution: The current crosstalk model in chip design is molded as background noise, as a Gaussian distribution. This approach is usually conservative on the throughput, and not actually represents the real distribution. In fact, the crosstalk is the nearby transmitting signals coupling onto the wireline of the receiver end. Thus, the channel media can be modeled as a multiuse channel with a multiple inputs and single vector output (MISO). We can detect the desired signal and crosstalk signals jointly, then subtracting the crosstalk signals in receive end. Almost all the high speed data transmission interconnection between (or inside) chip has the same power spectral density, and with the simple baseband transmission. Our approach will not increase much on complexity, but significantly improve the transmission performance, especially for next generation high speed chip design. This initial draft provides an overview of the tests that will be performed on the both up-channel and downstream channel circuitry for the 6.4Gbps HSS core on the Mistral testsite. (I) Characterization of up-channel Tx and Rx system level functional test (II) Characterization of channel performance test 1.1. Equipments and Resources Oscilloscope, Pattern Generator, Noise Generator, BERT, Specified Channel Representation Circuits, Evaluation Broad. Assist once with test setup and design software such as Lab View, building designed testbed and channel circuits. 1.2. Time Schedule and Resource Needs (beginning from 11/03) 1.2.1. Test Bed Set Up (a) Need Pill to work with me on test bed set up in first week (11/3/03 – 11/10/03) full time.
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